Generally, a PRAM (Phase-changeable memory device) has a transistor and a phase-change layer pattern. A PRAM may have one or more contacts to electrically connect the phase-change layer pattern and the transistor. One contact may connect to a source or drain region of the transistor, and the remaining contacts may connect and overlap the phase-change layer pattern.
Storing data in a PRAM typically requires high current density. When heavy current flows through the transistor and the contacts to the phase-change layer, the phase of the crystal structure of the phase-change layer pattern changes. The PRAM cell then stores either a “0” or “1” when this phase-change occurs.
Unfortunately, high current can lead to unwanted high power consumption. Increasing the contact resistance between the phase-change layer and the contact is a way to reduce the power consumption. Many methods for reducing area of the contacts have been proposed to increase the resistance and reduce the power consumption. Yet, as PRAMs become smaller, forming small contacts to the phase-change layer pattern generally becomes increasingly difficult. This difficulty arises because the reduction of design rules limit photolithography processes for defining contact images on photoresist layers. Furthermore, the limited photolithography process may decrease the flexibility of the PRAM fabrication processes.
In disclosing a method of making a programmable resistance memory element with a small contact area, U.S. Pat. Publication No. 2002/0197566 to Jon Maimom, et. al ('197566) presents one solution for increasing contact resistance. This solution is to use a silylation process to form small contact areas.
According to '197566, the method includes providing a first material layer, which may be formed using a conductive layer. A second material layer, a photoresist layer, is formed on the first material layer. The second material layer is partially removed, thereby forming a pattern on the first material layer. A silylation agent is deposited on the sidewalls and the upper surface of this photoresist pattern. Silicon atoms diffuse from the photoresist layer into the silylation agent forming the silylation layer.
The method further involves forming a third material layer, which is a photoresist layer, on the first material layer and the silylation layer. The third material layer is partially removed, thereby exposing the silylation layer between the second material layer and the third material layer. The silylation layer is removed. Using the third material layer and the second material layer as an etch mask, the first material layer is partially removed, thereby forming a narrow opening in the first material layer. A programmable resistance material is deposited in the narrow opening and contacts a lower electrode on a layer below the first layer. Thus, because the layer of programmable resistance is so narrow, the contact area between the programmable resistance material and the lower electrode is small. By decreasing the contact area with the silylation process, the contact resistance is increased and power consumption is reduced.
However, the '197566 solution can be expensive and increase fabrication time. Since the '197566 method includes a silylation process, two additional photolithography processes, and one additional etch for the formation of the opening, the method may increase production costs for a semiconductor device. Furthermore, the method may prolong fabrication time because the second and third material layers and the silylation layer typically are removed on different working lines of the processes.